This application claims the priority of Application No. 2002-154592, filed May 28, 2002 in Japan, the subject matter of which is incorporated herein by reference.
This invention relates to a semiconductor device (apparatus) including a memory circuit and a logic circuit, and a method for testing the same.
Conventionally, the Boundary-Scan method has been used for testing a semiconductor device, which is shown in Japanese Patent Publication, Kokai 2001-183420. According to the boundary-scan technique, the specification of the test is determined by, for example, IEEE1149.1. Therefore, the same test pattern signal can be used for a variety of semiconductor device made by different manufactures.
According to a conventional method of test for a semiconductor device, including a memory circuit it is required to carry out tests for the memory circuit and for another logic circuit independently or separately from each other. As a result, it spends a longer period of time to test a semiconductor device, including a memory circuit.
Accordingly, an object of the present invention is to provide a semiconductor device in which an operation test can be performed for a short period of time.
Additional objects, advantages and novel features of the present invention will be set forth in part in the description that follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
According to a first aspect of the present invention, a semiconductor device includes an external input terminal to which first and second input test signals are supplied; a memory circuit, in which a test operation is performed in accordance with the first input test signal to provide a first test result signal; a logic circuit, in which a test operation is performed in accordance with the second input test signal to provide a second test result signal; an external output terminal from which the first and second test result signals are outputted selectively; and a switch circuit which selectively couples the memory circuit and the logic circuit to the external input terminal and the external output terminal.
According to a second aspect of the present invention, a method for testing a semiconductor device, including the steps of inputting a first test signal for a memory circuit during a first period of time; performing a writing test operation of the memory circuit in accordance with the first test signal during a second period of time; and inputting a second test signal for a logic circuit and performing a test operation of the logic circuit during a third period of time, which is within the second period of time;
As described above, according to the present invention, the total test time for a semiconductor device is remarkably shortened.